This invention relates generally to semiconductor manufacture and more particularly to an improved interconnect for semiconductor wafers, and to a test method and system that employ the interconnect.
Semiconductor wafers must be tested during the manufacturing process to evaluate the electrical characteristics of the integrated circuits formed on the wafer. Standard tests for gross functionality are typically performed by probe testing the wafers using probe cards and wafer steppers. Other tests such as burn-in, and high speed testing are typically performed after the dice have been singulated and packaged. Among the tests performed are dynamic burn-in, input/output leakage, speed verification, opens, shorts, refresh and a range of algorithms to verify AC parameters.
In the past, burn-in and speed testing have been performed at the die level rather than at the wafer level. One reason that these test procedures are not performed at the wafer level is because the tests require interconnects with a large number of contact members and input/output paths to the wafer. For example, a wafer can include several hundred dice each having twenty or more bond pads. The total number of bond pads on the wafer can be in the thousands. For some tests procedures a contact member and input/output path must be provided to each bond pad. Even with wafer stepping techniques, conventionally formed interconnects, such as probe cards; usually do not include enough contact members (e.g., probes) to test dice having a large number of bond pads.
In addition to contact density limitations, force application and damage to the wafer must be minimized during the wafer testing procedure. In general, a large number of bond pads on the wafer will require that high contact forces be generated between the wafer and interconnect. The high contact forces can damage the wafer, particularly the bond pads that can have a thickness of only 1 xcexcm or less. Damage to thin film metal bond pads can also result from the necessity to penetrate the metal oxide layer on the bond pads to make a good electrical connection.
It would be advantageous for an interconnect to include contact members capable of testing a wafer with a large number of bond pads. This would permit both gross functionality as well as burn-in, dynamic burn-in, and high speed tests to be performed at the wafer level. It would also be advantageous to test all of the dice on the wafer simultaneously so that wafer stepping techniques do not need to be employed. This would decrease the time for testing and improve wafer throughput. Still further, it would be advantageous to be able to control the amount of contact force exerted on the wafer by an interconnect in order to minimize damage to the wafer and bond pads. In view of the foregoing, the present invention is directed to an improved interconnect and method for testing semiconductor wafers.
In accordance with the invention, an improved interconnect, method and system for testing semiconductor wafers are provided. The interconnect comprises a substrate having integrally formed contact members for establishing temporary electrical communication with contact locations (e.g., bond pads, test pads) on the wafer. For wafers with flat contact locations, such as thin film bond pads, the contact members comprise raised members with penetrating projections adapted to penetrate the contact locations to a limited penetration depth. For wafers with bumped contact locations, such as solder bumps, the contact members comprise indentations adapted to retain the bumped contact locations.
The interconnect includes a pressure sensing mechanism mounted to the substrate and adapted to monitor the contact forces between the interconnect and wafer. The pressure sensing mechanism can include a piezoresistive or piezoelectric layer in electrical communication with a resistance measuring device. The resistance measuring device can be a Wheatstone bridge formed on the substrate or externally mounted to a testing apparatus. In addition, the piezoelectric or piezoresistive layer can be segmented, such that each die on the wafer has an associated pressure sensing segment. In an alternate embodiment, the pressure sensing mechanism includes pressure detectors, such as microsensors, mounted within a base.
The contact members on the substrate include conductive layers in electrical communication with conductors formed on the substrate. The conductors can be formed on different levels of the substrate (i.e., multi level conductors) to provide high speed conductive paths to dense arrays of contact members without cross talk and capacitive coupling between the conductors. In addition, the conductors can be formed in electrical communication with an edge connector formed on the substrate.
Preferably the interconnect substrate comprises silicon, such that a thermal coefficient of expansion (TCE) of the interconnect matches that of the wafer. With a silicon substrate, the raised contact members can be formed using a bulk micro machining process. In addition, an SiO2 insulating layer can be formed on the substrate for electrically isolating the substrate from the contact members and conductors.
The indentation contact members can be formed on a silicon or a ceramic substrate. With a ceramic substrate the insulating layer is not required. In addition, concave depressions for the indentation contact members can be formed by laser ablating the substrate, and then depositing the conductive layers in the depressions.
The interconnect corresponds in size to the wafer being tested, and the contact members on the interconnect are formed in patterns that correspond to the patterns of the contact locations on the wafers. For some test procedures, such as dynamic burn-in and speed testing, the contact members can be configured to electrically contact every contact location (e.g., every bond pad) on the wafer. This permits an entire wafer to be tested without having to step the interconnect across the wafer. For other test procedures, such as static burn-in, the contact members can be configured to electrically contact only the Vss and Vcc contact locations on the wafer. Thus reduced contact forces are required between the wafer and interconnect, because fewer contact members are required.